(1) Field of the Invention
The present invention relates to a method of fabricating a metal-insulator-metal capacitor, and more particularly, to a method of forming a high capacitance metal-insulator-metal capacitor in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Capacitors are critical components in the integrated circuit devices of today. Both polysilicon and metal-insulator-metal (MIM) capacitors have been used in the art. The conventional MIM capacitor module which is inserted into the backend process of integrated circuit manufacturing results in a very low capacitance density. The capacitance density is proportional to the reverse of the dielectric thickness. Often, sophisticated additional metal and dielectric layers must be added for high capacitance density. FIG. 1 illustrates an example of a conventional MIM capacitor process. It is simple, but has a very low capacitance density. Bottom capacitor plate 30 is shown over semiconductor substrate 10. The metal bottom plate is covered by a thin oxide 32. Spin-on-glass material 34 fills the gaps between metal lines. A very thick oxide 36, more than about 1000 Angstroms in thickness and generally a few thousand Angstroms, forms the capacitor dielectric layer underlying the top plate electrode 40. The thick oxide is required for a low parasitic capacitance between the conducting layers and for good electrical isolation. In this example, the capacitance density F is approximately 10.sup.-17 farads/.mu.m.sup.2.
FIG. 2 illustrates an example of another conventional approach in which additional metal and thin oxide layers are added to improve capacitance density. A thin CVD oxide layer 38 is deposited over the bottom plate electrode 30. This oxide layer 38 has a thickness of approximately a few hundred Angstroms, for example about 500 Angstroms, and forms the capacitor dielectric. The metal layer 42 is formed over the capacitor dielectric. Then the sandwich dielectric layer comprising oxide 44, spin-on-glass 46, and oxide 48, is deposited over the metal layer 42. An additional metal layer 50 forms the upper plate electrode and contacts the lower metal layer 42 through a via opening. The metal layer 42 for circuit interconnection cannot be used directly as the upper electrode because of the thicker intermetal oxide required thereunder. In this example, the capacitance density F is approximately 6.times.10.sup.-16 farads/.mu.m.sup.2. It is desired to have a capacitance density in the range of 10.sup.-15 to 10.sup.-16 farads/.mu.m.sup.2.
U.S. Pat. Nos. 5,576,240 and 5,654,581 to Radosevich et al, U.S. Pat. No. 5,479,316 to Smrtic et al, U.S. Pat. No. 5,708,559 to Brabazon, U.S. Pat. No. 5,406,447 to Miyazaki, U.S. Pat. No. 5,741,721 to Stevens, U.S. Pat. No. 4,959,705 to Lemnios et al, and U.S. Pat. No. 4,971,924 to Tigelaar et al all disclose various methods of forming metal-insulator-metal capacitors. U.S. Pat. No. 5,589,416 to Chittipeddi teaches fabrication of a metal-oxide-polysilicon capacitor. U.S. Pat. No. 5,554,558 to Paterson et al discloses a very high integrity capacitor dielectric in a polysilicon to polysilicon or polysilicon to metal capacitor. U.S. Pat. No. 5,268,315 to Prasad et al teaches silicon nitride as a capacitor dielectric in the fabrication of a MIM capacitor.